1. Field of the Invention
This invention relates to a switching circuit device and particularly relates to, in a high-power switching circuit device, a switching circuit device, which is significantly improved in terms of electrostatic breakdown voltage and enables simplification of the inspection process.
2. Description of the Related Art
With a switching circuit device that is employed for an antenna switching application in a third-generation cellular phone terminal, FETs (Filed Effect transistors) must be serially connected in three stages in order to switch signals of approximately 26 dBm. This switching circuit device is called an SPDT (Single Pole Double Throw), uses a total of six FETs, and has the five external terminals of a common input terminal IN, output terminals OUT1 and OUT2, and control terminals Ctl-1 and Ctl-2.
FIGS. 10A and 10B are circuit diagrams showing an example of compound semiconductor switching circuit device of the conventional art. As shown in FIG. 10A, the switching circuit device includes a first FET set F1 and a second FET set F2, in each of which three FETs are connected serially. Also, a source electrode (or drain electrode) of FET1-1 of the first FET set F1 and a source electrode (or drain electrode) of FET2-1 of the second FET set F2 are connected to a common input terminal IN. And gate electrodes of the three FETs of the first FET set F1 are respectively connected via resistors to a common first control terminal Ctl-1 and three gate electrodes of the second FET set F2 are respectively connected via resistors to a second control terminal Ctl-2. Furthermore, a drain electrode (or source electrode) of FET1-3 of the first FET set F1 is connected to a first output terminal OUT1 and a drain electrode (or source electrode) of FET2-3 of the second FET set F2 is connected to a second output terminal OUT2. The control signals that are applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals and the FET set, to which a H level signal is applied, turns ON and transmits an input signal applied to the common input terminal IN to one of the output terminals. The resistors are disposed for the purpose of preventing the leakage of high-frequency signals from the gate electrodes to the first and second control terminals Ctl-1 and Ctl-2, which are DC potentials, that is, AC grounded.
FIG. 10B is a circuit diagram of the first FET set F1. A circuit diagram of the second FET set F2 is designed in the same manner. As illustrated, with the FET set F1, in which multiple stages are connected serially, the source electrode of FET1-1 is connected as a source S of the FET set F1 to the common input terminal IN, the respective gate electrodes of FET1-1, FET1-2, and FET1-3 are connected in common, as a gate G of the FET set F1, to the first control terminal Ctl-1, and the drain electrode of FET1-3 is connected as a drain D of the FET set F1 to the first output terminal OUT1.
FIG. 11 shows an example of a compound semiconductor chip in which compound semiconductor switching circuit devices are integrated.
Two FET sets, F1 and F2, for performing switching are disposed on a GaAs substrate. FET set F1 has, for example, FET1-1, FET1-2, and FET1-3 connected in series. FET set F2 has FET2-1, FET2-2, and FET2-3 connected in series. Resistors R1-1, R1-2, R1-3, R2-1, R2-2, and R2-3 are respectively connected to the six gate electrodes of the respective FET sets. Also, electrode pads 1, O1, O2, C1, and C2, respectively corresponding to the common input terminal IN, the output terminals OUT1 and OUT2, and the control terminals Ctl-1 and Ctl-2, are disposed at the periphery of the substrate. Also, a second-metal layer wiring, indicated by dotted lines, is a gate metal layer (Ti/Pt/Au) 20, formed at the same time the gate electrodes of the respective FETs are formed, and a third-metal layer wiring, indicated by solid lines, is a pad metal layer (Ti/Pt/Au) 30 for connection of the respective elements and pad formation. A first-metal layer as ohmic metal layer (AuGe/Ni/Au), which forms ohmic contact with the substrate, forms the source electrodes and drain electrodes of the respective FETs and forms the lead-out electrodes at both ends of the respective resistors, and is not illustrated in FIG. 11 since it overlaps with the pad metal layer.
Since the FET set F1 and the FET set F2 are positioned symmetrically with respect to the central line of the chip and are the same in layout, FET set F1 shall be described below. With FET1-1, a three-teeth-comb-shaped third-metal layer pad metal layer 130 parts, which extend from the upper side, comprise a source electrode 109 (or drain electrode) connected to the common input terminal pad I, and below this is disposed a source electrode 106 (or drain electrode) formed by the first-metal layer ohmic metal layer. Also, the three-teeth-comb-shaped third-metal layer pad metal layer 130 parts, which extend from the lower side, comprise a drain electrode 110 (or source electrode) of FET1-1, and below this is disposed a drain electrode 107 (or source electrode), formed by the first-metal layer ohmic metal layer. These electrodes are disposed in the form of engaged comb teeth and in between these, a gate electrode 105, formed of a second-metal layer gate metal layer 120, is disposed in the form of five comb teeth.
Channel regions are disposed below the parts at which the source electrode 109, the drain electrode 110, and the gate electrode 105 are disposed and these become the operating regions of FET1-1.
With FET1-2, the three comb teeth of the source electrode 106 (or drain electrode) that extend from the upper side are connected to the drain electrode 110 of FET1-1. Also, the three comb teeth of the drain electrode 110 (or source electrode) that extend from the lower side are connected to the source electrode 109 of FET1-3. The first-metal layer ohmic metal layer is disposed below these electrodes. These are disposed in the form of engaged comb teeth and in between these, the gate electrode 105, formed of the second-metal layer gate metal layer 120, is disposed in the form of five comb teeth.
With FET1-3, the three-teeth-comb-shaped third-metal layer pad metal layer 130 parts, which extend from the upper side, comprise the source electrode 109 (or drain electrode), and below this is disposed the source electrode 106 (or drain electrode) formed by the first-metal layer ohmic metal layer. Also, the three-teeth-comb-shaped third-metal layer pad metal layer 130 parts, which extend from the lower side, comprise the drain electrode 110 (or source electrode) that is connected to the output terminal pad O1, and below this is disposed the drain electrode 107 (or source electrode), formed by the first-metal layer ohmic metal layer. These electrodes are disposed in the form of engaged comb teeth and in between these, the gate electrode 105, formed of the second-metal layer gate metal layer 120, is disposed in the form of five comb teeth.
FIG. 12 shows a structure in which the above-described switching circuit device is assembled.
The semiconductor chip 67, which is shown in FIG. 11, is bonded by a silver paste or other conductive paste 70 onto an island 62f of a lead frame having five leads, and the respective terminal electrode pads of the semiconductor chip 67 are connected to the leads 62 by bonding wires 64. That is, the input terminal pad I is connected to a lead 62a, the control terminal pad C1 is connected to a lead 62b, the output terminal pad O1 is connected to a lead 62c, the control terminal pad C2 is connected to a lead 62d, and the output terminal pad O2 is connected to a lead 62e. The peripheral parts of the chip 67 are covered by a resin 75 that matches the shape of a molding die and the tips of the leads 62 are lead out to the exterior of resin 75. Such a package is called, for example, MCPH6 and has an external size of 2.1×2.0 mm2.
In this switching circuit device, the communications between the common input terminal IN and the control terminal Ctl-1, between the common input terminal IN and the control terminal Ctl-2, between the control terminal Ctl-1 and the output terminal OUT1, and between the control terminal Ctl-2 and the output terminal OUT2 correspond to the communications between the source electrode and the gate electrode of FET1-1, between the source electrode and the gate electrode of FET2-1, between the gate electrode and the drain electrode of FET1-3, and between the gate electrode and the drain electrode of FET2-3, respectively. As shall be described later, with these pairs, both the anodes and cathodes of the gate Schottky junctions of the FETs that are positioned at the ends of the respective FET sets are lead out to the exterior of the circuit. Though these electrode pairs have the problem of being weak in terms of electrostatic discharge, measures for improving the electrostatic breakdown voltage have not been taken in this art.
Also, though, for example, the electrostatic breakdown voltage can be increased somewhat by making the resistors connected to the control terminals larger, this method is not appropriate as it causes the switching time to become longer.